1. Field of The Invention
The present invention relates to electronics. More specifically, the present invention relates a dynamic flop design having a power down mode.
2. The Background
Dynamic flip-flops have been used in memories for many years. The advantage of using dynamic flip-flops over static flip-flops comes in the fact that they often have shorter delays, thus allowing the overall circuit to run faster. Typically dynamic flip-flops have a precharge phase and an evaluation phase.
A common problem occurs with dynamic flip-flops when static flip-flops are used to drive them. Conventional static flip-flops have uncertainty as to their output signals become stable. Therefore, the time required for the static flip-flop's output signals to become stable may extend into the evaluation phase of the dynamic flip-flop being driven by it.
One solution that has been offered for this problem is to provide a flip flop with a self-shut-off mechanism. FIG. 1 is a schematic diagram illustrating a dynamic flip-flop with a self-shut-off mechanism. The dynamic flip flop 50 includes a first input latch 52 with a shutoff circuit 54, a second input latch 56 with a shutoff circuit 58, and output latches 60 and 62. The substantially identical input latches 52, 56 are coupled to receive clock signal CK. Additionally, the first input latch 52 is coupled to receive the data input signal D. An inverter INV1 may also be coupled to receive the data input signal D. The second input latch 56 then receives the complement of the data input signal D from the inverter INV1.
The first input latch 52 provides an output signal to an input lead of the first output latch 60, through an output node OUT1N. Similarly, the second input latch 56 provides an output signal to an input lead of the second output latch 62, through an output node OUT2N. The shutoff circuits 54 and 58 have input leads connected to the output nodes, OUT2N and OUT2N, respectively. The substantially identical output latches 60 and 62 also have output leads connected to the Q and Q output terminals of the dynamic flip-flop 50.
This dynamic flip-flop operates as follows. During the logic low portion of each cycle of the clock signal CK, the dynamic flip-flop circuit 50 is in the precharge phase. The input latches 52 and 56 sample the data input signal D and the complemented data input D, respectively. The input latches 52, 56 each output the complement of its corresponding sample input signal. Consequently, if the data input signal D is at a logic high level, the first input latch 52 will output a logic low level on the output node OUT1N and the second input latch 56 will output a logic high level on the output node OUT2N. In response to the logic levels on the output nodes OUT1N and OUT2N, the output latches 60 and 62 will generate a logic high level Q output signal and a logic low level Q output signal, respectively.
The input latches 52 and 56 each output the complement of its corresponding sampled input signal. Consequently, if the data input signal D is at a logic high level, the input latch 52 will output a logic low level on the output node OUT1N and the input latch 54 will output a logic high level on the output node OUT2N. In response to the logic levels on the output nodes OUT1N and OUT2N, the output latches 60 and 62 will generate a logic high level Q output signal and a logic low level Q output signal, respectively.
In addition, in response to the logic low level on the output node OUT1N, the shutoff circuit 58 disables the input latch 56. As a result, the shutoff circuit 58 operates to prevent the input latch 56 from sampling the complemented data input signal D after the latch 56 causes the output node OUT1N transitions to a logic low level. Thus, the sampling window is approximately equal to the time needed by the input latch 52 to generate the logic low level on the output node OUT1N, plus the propagation delay of the shutoff circuit 58. This relatively short sampling window implements "edge-triggering" because the logic level is, in effect, sampled only at the rising edge of the clock signal CK. After being disabled during the evaluation phase, the logic levels at the output leads of the latches 52 and 56 are maintained throughout the remainder of the evaluation phase.
The first input latch 52 is implemented so that once the output node OUT1N is discharged (i.e., when the input latch 52 receives a logic high level data input signal D), a subsequent high-to-low transition of the data input signal D does not cause the logic level at the output node OUT1N to change. Alternatively, the shutoff circuit 54 can also monitor the logic level on the output node OUT1N and disable the first input latch 52 in response to the logic level transitioning to a logic low level.
Conversely, if at the start of the evaluation phase the data input signal D is at a logic low level, the first input latch 52 will output a logic high level on the output node OUT1N and the second input latch 56 will output a logic low level on the output node OUT2N. In response to the output signals on the output nodes OUT1N and OUT2N, the output latches 60 and 62 will provide a logic low level Q output signal and a logic high level Q output signal, respectively. The logic low level at the output node OUT2N also causes the shutoff circuit 54 to disable the first input latch 52, thereby helping implement the edge-triggered feature of the dynamic flip-flop circuit 50.
The input latch 52 includes p-channel transistors PC1 and K2, n-channel transistors S1, N1 and EVAL, and inverters INV2 and INV3. The n-channel transistor S1 and the inverters INV2 and INV3 implement the shutoff circuit 54.
The p-channel transistor PC1 has its gate coupled to receive the clock signal CK, its source coupled to a VDD voltage source (i.e, the VDD rail) and its drain connected to the output node OUT1N. The output node OUT1N is also connected to the drain of the n-channel transistor S1. The gate of the n-channel transistor S1 is coupled to the output node OUT2N through series connected inverters INV2 and INV3, where the output lead of the inverter INV2 is connected to the gate of the n-channel transistor S1, and the input lead of the inverter INV3 is connected to the output node OUT2N. The source of the n-channel transistor S2 is connected to the drain of the n-channel transistor N1. The n-channel transistor N1 has its gate coupled to receive the data input signal D, and its source connected to the drain of the n-channel transistor EVAL at the node CGND. The n-channel transistor EVAL has its gate coupled to receive the clock signal CK and its source coupled to a VSS voltage source (i.e., the VSS rail).
The second input latch 56 includes p-channel transistors K1 and PC2, n-channel transistors S2 and N2, and inverters INV4 and INV5. The second input latch 56 shares the n-channel transistor EVAL with the first input latch 52. In addition, the n-channel transistor S2 and the inverters INV4 and ISV5 implement the shutoff circuit 58. The second input latch 56 is substantially identical to the first input latch 52, except that the second input latch 56 is implemented with the transistors PC2, K1, S2 and N2 in place of the transistors PC1, K2, S1 and N1, and with the inverters INV4 and INV5 in place of the inverters INV2 and INV3. In addition, the second input latch 56 receives the complemented data input signal Q through the inverter INV1 at the gate of the n-channel transistor N2.
The first output latch 60 includes an inverter INV6 and a n-channel transistor N3. The input lead of the inverter INV6 is connected to the output node OUT1N. The output lead of the inverter INV6 is connected to the Q output terminal of the dynamic flip-flop circuit 50 and the gate of the n-channel transistor N3. The n-channel transistor N3 has its source connected to the VSS voltage source, and its drain connected to the input lead of the inverter INV6.
The second output latch 62 includes an inverter INV7 and a n-channel transistor N4. The input lead of the inverter INV7 is connected to the output node OUT2N. The output lead of the inverter INV7 is connected to the Q output terminal of the dynamic flip-flop circuit 50 and the gate of the n-channel transistor N4. The n-channel transistor N4 has its source connected to the VSS voltage rail, and its drain connected to the input lead of the inverter INV7.
FIG. 2 is a timing diagram illustrating the operation of the dynamic flip-flop circuit of FIG. 1. Referring to FIGS. 1 and 2 together, the dynamic flip-flop circuit 50 of FIG. 1 operates as follows. When the clock signal CK is at a logic low level, the dynamic flip-flop circuit 50 is in the precharge phase, as indicated by the waveform 101. Consequently, the precharge devices (i.e., the p-channel transistors PC and PC2) are turned on and the n-channel transistor EVAL is turned off. Because the n-channel transistor EVAL is off, the p-channel transistors PC and PC2 pull up the voltage at the output nodes OUT1N and OUT2N to approximately the VDD rail voltage, thereby precharging the output nodes OUT1N and OUT2N. Thus, the keeper devices (i.e., p-channel transistors K1 and K2) are turned off. The logic high level at the output nodes OUT1N and OUT2N causes the shutoff devices (i.e., n-channel transistors S1 and S2) to turn on, after the two inverter delays incurred by the two series connected inverters in each of shutoff circuits 54 and 58.
In addition, the logic high level at the output nodes OUT1N and OUT2N, respectively, propagate through the inverters INV6 and INV7, causing the Q and Q output signals to be at a logic low level during the precharge phase, as indicated by the solid line portions of the waveforms 103 and 105. The logic low Q and Q output signals cause the n-channel transistors N3 and N4 to be off. In this example, the Q output signal was at a logic low level (with the Q output signal being at a logic high level) during the previous evaluation phase. The dashed line portions 103A and 105A represent the Q and Q output signals resulting from the Q output signal being at a logic high level during the previous evaluation phase.
When the clock signal CK transitions to a logic high level (i.e., low-to-high), the n-channel transistor EVAL is turned on, which places the dynamic flip-flop circuit 50 in the evaluation phase. The n-channel transistor EVAL pulls down the voltage at the node CGND to approximately the VSS rail voltage. In addition, the low-to-high transition of the clock signal CK also turns off the precharge devices PC1 and PC2.
The data input signal D is provided to the dynamic flip-flop circuit 50 such that it is stable before the low-to-high transition, as shown by waveform 107. The data input signal D need not be stable except at around the beginning of the evaluation phase. If the data input signal D is at a logic high level when the evaluation phase begins, the n-channel transistor N1 is turned on while the n-channel transistor N2 is turned off. Because the n-channel transistor N1 is on, the voltage at the output node OUT1N is pulled to about the VSS rail voltage through the n-channel transistors S1, N1 and EVAL. Thus, the input latch 52 provides a logic low output signal at the output node OUT1N, which turns on the p-channel transistor K1 to help keep the voltage at the output node OUT2N at a logic high level. The logic low level at the output node OUT1N also propagates through the inverter INV6. As a result, the Q output signal transitions from low-to-high, as shown by portion 109 of the waveform 103. The logic high level of the Q output signal turns on the n-channel transistor N3, which helps to further pull down the voltage at the output node OUT1N.
The logic low level at the output node OUT1N also propagates through the inverters INV4 and INV5, resulting in the gate voltage X1 of the n-channel transistor S2 being driven to a logic low level. Consequently, the shutoff device S2 is turned off. As a result, the second input latch 56 is disabled from sampling the voltage of the complemented data input signal D . Because the n-channel transistor S2 is off, the second input latch 56 now cannot discharge the output node OUT2N even if the data input signal D were to subsequently transition to a logic low level during this evaluation phase. Thus, the Q output signal remains at a logic low level, as indicated by the portion 111 of the waveform 105. Further, if the data input signal D were to transition to a logic low level after the output node OUT1N was discharged, the n-channel transistor N1 would be turned off, but the n-channel transistor N3 keeps the voltage at the output node OUT1N at a logic low level.
The two stage design of the dynamic flip-flop circuit 50 greatly increases the speed of the flip-flop circuit compared to conventional static flip-flop designs. However, this design has a major drawback in that it wastes power. During each cycle, power is consumed due to the charging and discharging of dynamic flops. While this may be efficient enough for memories that are frequently accessed, for memories that are less frequently accessed there is a tremendous waste of power. In Content Addressable Memories, a look-up operation is not always used, or at least not used on every cycle. Yet, if the circuit design described above was used, power would be consumed on every cycle. What is needed is a design which eliminates the delay associated with static flip-flops, yet does not waste as much power as prior art dynamic flip-flops do.